电子工程专辑

FPGA集成数据缓冲器与分离FIFO或多端口存储器的比较

对于那些时钟频率低于100 MHz、存储器密度低于512K数据缓冲应用来说，将该设计集成到一个单 FPGA中常常能够提供最理想的解决方案。然而，随着缓冲存储器的需求增长和时钟频率的增加，设计者会发现采用分立 FIFO和多端口存储器的高性能和低成本特性将会 ...
Design-Reuse

Building an FPGA FIFO without using logic recourses

Today, FPGA designers are using these flexible devices to perform everything from simple glue logic tasks to implementing complicated system on a chip (SoC) functions. The efficiency and ease of ...
Business Wire

DVCon Europe “Must See”: Aldec Tutorial and Demonstration on Adopting Easier UVM to ...

MUNICH--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for system and ASIC designs, is supporting the second Annual DVCon Europe ...